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Senior ASIC Design Engineer -Risc-V / UVM

📍 San Jose, CA 🕒
Work Model
📍 San Jose, CA
Employment
💼 Full-Time Direct
Recruitment Type
🛡️ Direct to HR Pipeline
🛡️
Human-Verified Opening: Inspected by Sarah Jenkins, CIPD • RemoteVault Editorial Team. Authenticated directly from European Recruitment's hiring pipeline • Zero recruiter markups or candidate fees. Verification Standards →

📋 Role Overview & Responsibilities

Senior ASIC Design Engineer- RTL Design / UVM

We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking for Senior ASIC Verification Engineer to join their team in California.

If this is you please continue reading below!

Responsibilities

Ensure the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks.SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and assembly diag validation)Architect and implement complex RTL designs.Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances.

Qualifications

5+ years of ASIC design experience, RTL logic DesignKnowledge of ARM/MIPS/RISC-V Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operationFamiliarity with AMBA/APB/AXI ProtocolFamiliarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ....Excellent Verilog/System Verilog programming skills.Experience with UVM (or similar).

Keywords: UVM / ASIC /System Verilog / Verilog / Python / Perl/ RTL Design

If interested Apply via LinkedIn, or send your CV to fm@eu-recruit.com

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Frequently Asked Questions

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This position is located in San Jose, CA with potential relocation and sponsorship assistance depending on candidate qualifications.

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