Senior Physical Design Engineer
📋 Role Overview & Responsibilities
About Us:We are representing Sivaltech (www.sivaltech.com), a design services company headquartered in Milpitas, CA. We provide complete end-to-end solutions for ASIC/FPGA Design both in Digital/Analog which includes RTL Design & Implementation, Functional Verification, Physical Design, AMS Verification, Layout Design, and circuit design, Embedded Software.
Sivaltech is proud to be an Equal Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex, age. Sivaltech is committed to providing reasonable accommodation for candidates in our recruiting process.
Role Description:The Senior Physical Design Engineer position is a full time or contract role located in Santa Clara, CA. Your day-to-day responsibilities will include ensuring to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification.
Responsibilities:You will support floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
Qualifications To be a successful candidate for this role, we require:Minimum of 7-10+ years of experience in Physical design.Proficiency in Python and/or Perl is required. Additional languages are a plus.Versatility with scripts to automate design flow, and quality checks.Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications.Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applicationsExperience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation.
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This position is located in Santa Clara, CA with potential relocation and sponsorship assistance depending on candidate qualifications.
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